Method for an integrated circuit contact

ABSTRACT

A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/136,544,filed May 1, 2002, pending, which is a continuation of application Ser.No. 09/569,578, filed May 10, 2000, now U.S. Pat. No. 6,414,392, issuedJul. 2, 2002, which is a divisional of application Ser. No. 09/099,047,filed Jun. 17, 1998, now U.S. Pat. No. 6,221,779, which is acontinuation of application Ser. No. 08/786,482, filed Jan. 21, 1997,now U.S. Pat. No. 5,858,877, which is a continuation of application Ser.No. 08/626,651, filed Apr. 1, 1996, now U.S. Pat. No. 5,651,855, whichis a continuation of application Ser. No. 08/259,187, filed Jun. 13,1994, abandoned, which is a continuation-in-part of application Ser. No.07/921,320 filed Jul. 28, 1992, abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention, relates generally to processes for manufacturing ultralarge scale integrated circuits (ULSICs) and more particularly to aself-aligned process for simultaneously enhancing the achievable devicepacking density, device reliability and yields during such manufacture.

In the manufacture of ultra large scale integrated circuits, such as 4megabit and up dynamic random access memories (DRAMs), it has been oneprior art approach to use an inlaid, fully integrated wiring technologywhich is known in the integrated circuit manufacturing arts as “DualDamascene” technology. This approach to ULSIC electrical contactdevelopment is described in some detail in Cronin, et al., U.S. Pat. No.5,126,006 and in an article by Carter W. Kaanta, et al. entitled “DualDamascene: A ULSIC Wiring Technology,” IBM General Technology Division,Essex Junction, Vt., VMIC Conference, Jun. 11-12, 1991, at pp. 144-152.

This Dual Damascene processing for etching troughs through insulatinglayers formed on silicon substrates utilizes, among other things, firstand second successive etching steps in order to arrive at an ultimatetrough and contact hole geometry within surrounding insulating layersformed on the surface of a silicon wafer. The first etch step forms thetrough down to a controlled depth within the surface insulating layers.The second etch step extends the depth of the trough down to the activedevices within the silicon substrate to form the contact hole. Onedisadvantage of using the above described Dual Damascene approach isthat the photoresist etch mask required for the second etch step must beprecisely aligned with respect to the trough opening formed by the firstetch step. The requirement for precise alignment of the second etch maskimposes an upper threshold on the maximum achievable packing density,reliability and yields that can be reached using the above DualDamascene process. In addition, present techniques do not allow the etchof the interconnect trough to be controlled independent of the etch ofthe stud or contact hole.

It is the solution to these problems to which the present invention isdirected.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, it has been discovered thatthe above problem of precise second etch mask alignment with respect tothe first formed trough opening can be significantly reduced by theemployment of an etch stop layer on the surface of the insulating layer.The width dimension of an opening in the etch stop layer is madecoextensive with the width dimension of the desired trough opening to beformed within the insulating layer. Then, the etch stop layer is used incombination with an etchant to define the trough opening within theinsulating layer. Next, a photoresist etch mask is formed on the surfaceof the etch stop layer and has an opening therein defined bypredetermined width and length dimensions dependent upon the desiredtrough geometry. However, since the photoresist mask is formed above theetch stop layer, the alignment of its width dimension is not nowcritical inasmuch as the etching action for increasing the depth of aportion of the trough to complete formation of the stud or contact holeis confined, or self-aligned, by the opening in the etch stop layer.Thus, as this second etching step of the insulating layer continues onto the silicon substrate surface, its width dimension remains constant.Also, because the interconnect trough is completely formed in the firstetch, the trough can be and is masked during the second etch that formsthe stud or contact hole. The etch that forms the contact hole can,therefore, be controlled independent of the etch that forms the trough.

Next, the photoresist mask is removed and the completed trough andcontact hole is filled with a selected metal such as tungsten. Finally,and optionally, the etch stop layer can be either retained in place orremoved and the tungsten layer is chemically and mechanically polishedusing known CMP processes back to a depth substantially coplanar withthe surface of the etch stop layer when the etch stop layer is retainedin place. Optionally, surface contact pads may be formed on top of thecompleted metal pattern. Also optionally, the etch stop layer removalstep can be carried out prior to the tungsten deposition step, andblanket etching of metal can be used instead of CMP processes.

Accordingly, it is an object of the present invention to provide a newand improved self-aligning process for making electrical contacts in themanufacture of high density integrated circuits.

Another object of this invention is to provide a new and improvedprocess of the type described which represents a novel alternative withrespect to the above described Dual Damascene process.

Another object of this invention is to provide a new and improvedprocess of the type described which operates to increase maximumachievable device packing density in the manufacture of integratedcircuits.

Another object of this invention is to provide a new and improvedelectrical contract forming process of the type described which enhancesdevice reliability and device yields.

Another object of this invention is to provide a new and improvedprocess of the type described which may be repeated through a pluralityof stacked dielectric layers such as SiO₂ to thereby form a multi-levelmetal integrated circuit.

Briefly summarized, and commensurate in scope with the broad claimsfiled herein, the present process of forming electrical contacts in themanufacture of integrated circuits includes the steps of: forming aninsulating layer on the surface of a silicon substrate; forming an etchstop layer on the surface of the insulating layer; forming an opening inthe etch stop layer; etching through the opening to a first trough depthinto the insulating layer exposed by the opening in the etch stop layer;forming a photoresist etch mask on the surface of the etch stop layerand in a portion of the trough; continuing to etch the exposed portionof the insulating layer until reaching the surface of the siliconsubstrate to thereby form the contact or stud hole; removing thephotoresist mask; and filling the trough and hole thus formed with aselected metal such as tungsten. In a preferred embodiment of theinvention, chemical-mechanical polishing processes are used to remove aportion of the selected metal back to a depth coplanar with the surfaceof the etch stop layer or surface of the insulating layer.

The above brief summary of the invention, together with its attendantobjects, advantages and novel features will become better understoodwith reference to the following description of the accompanyingdrawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1 through 10 are a series of schematic cross section diagramsillustrating the sequence of process steps used in a preferred processembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is shown a silicon substrate 10 in whichone or more active device regions 12 have been formed using conventionaldiffusion or ion implantation doping techniques together withconventional photolithographic masking and etching procedures.Typically, a relatively insulating layer 14, preferably made of silicondioxide, will be formed on the surface of the silicon substrate 10 usinglow temperature chemical vapor deposition processes and preferably aknown tetraethylorthosilicate (TEOS) process. Next, a thin etch stoplayer 16 is formed to a thickness of about 500-1000 angstroms on thesurface of the insulating layer 14. Etch stop layer 16 may be made ofany suitable material such as silicon nitride, Si₃N₄, or titanium oxide,TiO, or aluminum oxide, Al₂O₃.

An opening is then formed in etch stop layer 16 to expose portions ofinsulating layer 14 at locations of desired trough patterns. In thepreferred embodiment, and referring now to FIG. 2, a first photoresistmask 18 is formed on the surface of the etch stop layer 16, and anopening 20 is formed in the photoresist mask 18 using conventionalphotolithographic masking and etching procedures in order to expose agiven area 22 of the etch stop layer 16. Then, as shown in FIG. 3, anopening is first etched as indicated at 24 in the etch stop layer 16using an etchant such as CHF₃ and CF₄, and the first photoresist mask 18in FIG. 3 may be left in place during etching down to a first desireddepth to form trough 26 within the insulating layer 14. Once the trough26 depth has been reached, then the first photoresist mask 18 in FIG. 3is removed as shown in FIG. 4. The etch stop layer 16 of either siliconnitride, titanium oxide, aluminum oxide or other equivalent denseinorganic insulating material will be quite suitable to serve as an etchmask during the etching of the insulating layer 14 in the geometry shownin FIGS. 3 and 4.

Referring now to FIG. 5, a second photoresist mask 28 having an opening30 therein is formed on the surface of the etch stop layer 16. Thissecond photoresist mask 28 will serve to mask against etching carriedout using state of the art reactive ion etching (RIE) techniques.Opening 30 in second photoresist mask 28 has a width dimension, W, andneed not be precisely aligned with the corresponding width dimension ofthe trough 26 opening because, during this etching process, etch stoplayer 16 will serve to mask against the vertical ion bombardment exceptin the region of the trough 26. Such ion bombardment and etching willcontinue etching through the SiO₂ insulating layer 14 until reaching theactive device region 12 to thereby produce the contact hole 33 indicatedin FIG. 6. As seen in FIG. 6, the length dimension of the contact hole33 extends to a back wall 34 of the insulating layer 14, and this backwall 34 is aligned with the back wall 36 of the second photoresist mask28.

Referring now to FIG. 7, the second photoresist mask 28 in FIG. 6 hasbeen removed to show the completed trough and hole geometry consistingof a first depth at the top wall 38 which extends into the devicestructure of FIG. 7 along the length of the top wall 38 and the secondgreater depth at exposed surface 32. There is no criticality of maskalignment of the width dimension W of the photoresist mask 28 with thewidth dimension of the vertical trough being etched. However, thealignment of the contact hole 33 length dimension as defined by the backwall 36 of the photoresist mask 28 in FIG. 6 still remains critical todefining the precisely desired device geometries for the integratedcircuits being manufactured. It should be noted that, as illustrated,the insulating layer 14 has a first opening having a first length L₁ anda first width W₁, a second opening connected to the first openinglocated therebelow having a second length L₂ which is less than thelength L₁ and a second width W₂ which is one of at least equal to thefirst width W₁ of the first opening and greater than the first width W₁of the first opening. Further, the etch stop layer 16 located over theinsulating layer 14 has a third opening which is located above the firstopening in the insulating layer 14 and connected to the first openinghaving third length L₃ at least equal to the first length L₁ of thefirst opening in the insulating layer 14 and a third width W₃ being oneof at least equal to the first width W₁ of the first opening of theinsulating layer 14 and greater than the first width W₁ of the firstopening in the insulating layer 14.

Referring now to FIG. 8, the exposed surface 32 and top wall 38 in FIG.7 and the top surfaces of the etch stop layer 16 are covered withadhesion layer 40, and then as shown in FIG. 9, a metal layer 42 isdeposited on the outer surface of the adhesion layer 40. This metallayer 42 will preferably be tungsten, copper or silver which is laiddown using conventional metal deposition processes. Adhesion layer 40,preferably made of titanium nitride, is sputter deposited on insulatinglayer 14 and etch stop layer 16 to improve bonding with metal layer 42.Frequently, it will be desired to then polish or etch back metal layer42 so that the ultimate top surface of the selected metal layer 42 iscoplanar with the top surface of the etch stop layer 16 as shown in FIG.10.

Optionally, the etch stop layer 16 can be used as a mask during etchingof the metal layer 42 so that the metal layer 42 can be etched throughopening 24 in etch stop layer 16 down to and coplanar with the topsurface of insulating layer 14. Etch stop layer 16 would then beremoved. The etch stop layer 16 may also be removed prior to forming theadhesion and metal layers 40 and 42, respectively. Also optionally,surface contact pads or interconnects (not shown) may be made on top ofor leading into the planarized metallization-filled troughs describedabove.

Various modifications may be made in and to the above describedembodiment without departing from the spirit and scope of thisinvention. For example, the present invention is in no way limited bythe particular materials or layer thicknesses described above which areonly exemplary of certain typical materials and layer thicknesses usedin existing ULSIC semiconductor fabrication processes. In addition, theetch stop layer may be either removed or retained in place after thevertical trough forming process has been completed. Furthermore, thepresent invention is not limited to the electrical interconnectionthrough a single layer of dielectric material, e.g. SiO₂, as shown inFIG. 10 and may instead be used in various types of multi-levelmetallization processes such as those shown, for example, in co-pendingapplication Ser. No. 07/775,744, U.S. Pat. No. 5,204,286 of Trung T.Doan entitled “Method of Making Self-Aligned Contacts and VerticalInterconnects to Integrated Circuits and Devices Made Thereby,” filedOct. 15, 1991, assigned to the present assignee and incorporated hereinby reference. Accordingly, these and other process and devicemodifications are clearly within the scope of the following appendedclaims.

1. A method of forming an opening in a layer of a semiconductor devicein a process, comprising: providing a first set of etching parameterswith a first resist mask over said layer of said semiconductor device;etching said layer according to said first set of etching parameters;removing said first resist mask; providing a second set of etchingparameters with a second resist mask, wherein said providing a secondset of etching parameters occurs after said removing said first resistmask; and etching said layer according to said first and second sets ofetching parameters.
 2. The method in claim 1, further comprisingretaining said first set of etching parameters after said removing saidfirst resist mask.
 3. The method in claim 2, wherein said retaining saidfirst set of etching parameters comprises: providing an etch stopmaterial between said first resist mask and said layer; etching saidetch stop according to said first set of etching parameters; andretaining said etch stop during said etching of said layer according tosaid first and second sets of etching parameters.
 4. A process forforming an opening in a layer of a semiconductor device, comprising:providing a first set of etching parameters with a first resist maskover said layer of said semiconductor device; etching said layeraccording to said first set of etching parameters; removing said firstresist mask; providing a second set of etching parameters with a secondresist mask, said providing a second set of etching parameters occursafter said removing said first resist mask; and etching said layeraccording to said first and second sets of etching parameters.
 5. Themethod in claim 4, further comprising retaining said first set ofetching parameters after said removing said first resist mask.
 6. Themethod in claim 5, wherein said retaining said first set of etchingparameters comprises: providing an etch stop material between said firstresist mask and said layer; etching said etch stop according to saidfirst set of etching parameters; and retaining said etch stop duringsaid etching of said layer according to said first and second sets ofetching parameters.
 7. A method of forming an opening in a layer of asemiconductor device using a first resist mask, comprising: determininga first set of etching parameters for use with the first resist mask;etching said layer according to said first set of etching parameters;removing said first resist mask; providing a second set of etchingparameters with a second resist mask, said providing a second set ofetching parameters occurs after said removing said first resist mask;and etching said layer according to said first and second sets ofetching parameters.
 8. The method in claim 7, further comprisingretaining said first set of etching parameters after said removing saidfirst resist mask.
 9. The method in claim 8, wherein said retaining saidfirst set of etching parameters comprises: providing an etch stopmaterial between said first resist mask and said layer; etching saidetch stop according to said first set of etching parameters; andretaining said etch stop during said etching of said layer according tosaid first and second sets of etching parameters.
 10. A method forforming an opening in a layer of a semiconductor device using a firstresist mask, comprising: using a first set of etching parameters withthe first resist mask over the layer of the semiconductor device;etching said layer according to said first set of etching parameters;removing said first resist mask; using a second set of etchingparameters with a second resist mask, the use of the second set ofetching parameters occurring after said removing said first resist mask;and etching said layer according to said first and second sets ofetching parameters.
 11. The method in claim 10, further comprisingretaining said first set of etching parameters after said removing saidfirst resist mask.
 12. The method in claim 11, wherein said retainingsaid first set of etching parameters comprises: providing an etch stopmaterial between said first resist mask and said layer; etching saidetch stop according to said first set of etching parameters; andretaining said etch stop during said etching of said layer according tosaid first and second sets of etching parameters.
 13. A formation methodfor forming an opening in a layer of a semiconductor device using afirst resist mask, comprising: using a first set of etching parameterswith the first resist mask over said layer of said semiconductor device;etching said layer according to said first set of etching parameters;removing said first resist mask; using a second set of etchingparameters with a second resist mask after said removing said firstresist mask; and etching said layer according to said first and secondsets of etching parameters.
 14. The method in claim 13, furthercomprising retaining said first set of etching parameters after saidremoving said first resist mask.
 15. The method in claim 14, whereinsaid retaining said first set of etching parameters comprises: providingan etch stop material between said first resist mask and said layer;etching said etch stop according to said first set of etchingparameters; and retaining said etch stop during said etching of saidlayer according to said first and second sets of etching parameters. 16.A process method for forming an opening in a layer of a semiconductordevice using at least a first mask, comprising: determining a first setof etching parameters for use with the first resist mask over said layerof said semiconductor device; etching said layer according to said firstset of etching parameters; removing said first resist mask; determininga second set of etching parameters with a second resist mask to be usedafter said removing said first resist mask; and etching said layeraccording to said first and second sets of etching parameters.
 17. Themethod in claim 16, further comprising retaining said first set ofetching parameters after said removing said first resist mask.
 18. Themethod in claim 17, wherein said retaining said first set of etchingparameters comprises: providing an etch stop material between said firstresist mask and said layer; etching said etch stop according to saidfirst set of etching parameters; and retaining said etch stop duringsaid etching of said layer according to said first and second sets ofetching parameters.